Integrated circuits and chips have become increasingly complex, with the speed and capacity of chips increasing tremendously. This increase has resulted from advances in design software, fabrication technology, semiconductor materials, and chip design. An increased density of transistors per square centimeter and faster clock speeds, however, make it increasingly difficult to specify and design a chip that performs as specified. The demand for complex custom-designed chips (such as ASICs) has increased with the increasing variety of microprocessor-driven applications and products, yet designing such chips are costly and time consuming.
Integrated structured programmable platforms with serialization/deserialization (SERDES) technology have set a new performance standard for applications that require wide bandwidth capability. Many custom designs utilize SERDES technology to increase system bandwidth and reduce overall system costs. SERDES technology addresses the critical issues that alleviate the I/O bottleneck. The technology compresses slower-speed parallel data into much faster serial data. For example, in a networking application, the serializer in the SERDES block converts 400 MHz parallel data coming from inside the network card to 3.125 Gbps serial data as output to the backplane bus. The deserializer in another SERDES block then retrieves the serial data from the bus and converts it back to slower parallel data.
Conventionally, SERDES cores in ASIC, ASIC platform, and other programmable platforms designs have been implemented to utilize simulation and measurement through probing of the high speed signal to support design, test, and debugging systems. The measurement typically includes measuring the “eye” of the signal at the transmitter, the receiver, and at various points in the transmission path. This allows the engineer to measure jitter and eye height.
High speed SERDES cores have been introduced to operate without visible, or with very small eye openings, relying on signal processing techniques to open the “eye” and recover the data. However, there are many issues to design, test and debug systems involving high speed SERDES cores due to the high speed, mixed signal circuitry involved, and the stringent electronically specifications which they have to meet. Furthermore, as the transmission rates increase, it is increasingly difficult to relate the measured signal at the semiconductor package balls to the signal actually seen at the SERDES receiver on the silicon. The additional impedance and discontinuities of the package and bonding may also impact the signal seen, thus the engineer is unable to “see” these effects as they occur inside the package. In both cases, it is extremely difficult to test and debug such a system through measurement as in one case, the signal is not readily discernible as such in the external probes while in the other case the actual signal may not be probed internal to the chip during normal operation.
One possible solution is to build a probe or measurement system (e.g. a smart oscilloscope, or the like) that has signal processing capabilities as well, and may perform the signal processing to recover the data stream from the probed signal, and then display the raw and recovered signals. However, it does not address the effect of the package on the signal. Further, it assumes that all SERDES will perform identical signal processing, which is unrealistic. It is well known to the art that such a scope may not be calibrated with all possible SERDES cores and technologies.
Other solutions conventionally used are external and internal loopbacks, as well as reverse loopback. Referring now to FIG. 1, a block diagram of SERDES core 100 with various loopbacks is shown. An external loopback 102, 104 takes the data transmitted out of an ASIC's SERDES and physically wires it to the receiver of the same SERDES. This is a good test of complete operation of the transmitter and receiver SERDES silicon all the way through the core and out the package. However, this test works with a single SERDES in a test bed only. Actual system operation is not possible as the SERDES is only able to send test data to itself. This also does not allow testing between different chips or types of chips, as the loopback is to the same chip and same SERDES. Although this is a useful technique, it may not be useful when the problem being investigated only occurs in full system operation. Internal loopbacks are quite similar, but will “loop back” the transmitted data at some point prior to going off the die. The loopback may be at an analog or digital poll in the SERDES. It is typically used for debugging and testing the SERDES itself rather than the system in which it is instantiated.
Reverse loopbacks 106 include taking a received signal end looping it back out to the transmit port of the same SERDES (rather than taking the output of the transmitter and looping it to the receiver). As with the loopback methods described above, this may occur at several points, including a raw loopback, looping back after recovering, and retiming the data, or even taking the digital version of the recovered data and sending it back out all the way through the transmit SERDES. However, the Reverse loopbacks method has been utilized in limited ways. By looping back the receive data to the transmit port, the transmit port is no longer useful in a system environment, hence the Reverse loopbacks method is difficult or impossible to use in a full system test without adding extra unused SERDES paths.
In both loopback methods, loopbacks do not support system testing, as they take up either a receiver or a transmit SERDES port. In addition, neither exposes the internal nature of the signal to the external test point. Basically, the probe at the test point sees the output of a transmit SERDES port, not the processed, or partially processed received signal.
Therefore, it would be desirable to provide a method and system for exposing the processed or partially processed received signal at various external test points for a system involving high speed SERDES cores.